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 MM74HC393 Dual 4-Bit Binary Counter
September 1983 Revised January 2005
MM74HC393 Dual 4-Bit Binary Counter
General Description
The MM74HC393 counter circuits contain independent ripple carry counters and utilize advanced silicon-gate CMOS technology. The MM74HC393 contains two 4-bit ripple carry binary counters, which can be cascaded to create a single divide-by-256 counter. Each of the two 4-bit counters is incremented on the HIGHto-LOW transition (negative edge) of the clock input, and each has an independent clear input. When clear is set HIGH all four bits of each counter are set to a low level. This enables count truncation and allows the implementation of divide-by-N counter configurations. Each of the counters outputs can drive 10 low power Schottky TTL equivalent loads. This counter is functionally as well as pin equivalent to the 74LS393. All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Features
s Typical operating frequency: 50 MHz s Typical propagation delay: 13 ns (Ck to QA) s Wide operating supply voltage range: 2-6V s Low input current: <1 A s Low quiescent supply current: 80 A maximum (74HC Series) s Fanout of 10 LS-TTL loads
Ordering Code:
Order Number MM74HC393M MM74HC393SJ MM74HC393MTC MM74HC393N Package Number M14A M14D MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
(c) 2005 Fairchild Semiconductor Corporation
DS005337
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MM74HC393
Absolute Maximum Ratings
(Note 2) (Note 1) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260C (Note 4)
VCC 2.0V 4.5V 6.0V VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| 20 A 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT| 20 A 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN = VCC or GND IOUT = 0 A 6.0V VIN = VCC or GND 4.5V 6.0V 6.0V 4.5V 6.0V 2.0V 4.5V 6.0V
Recommended Operating Conditions
Min Max 6 VCC Units V V Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT ) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 600 mW 500 mW 1000 500 400 ns ns ns 0 2
-0.5 to +7.0V -1.5 to VCC +1.5V -0.5 to VCC +0.5V 20 mA 25 mA 50 mA -65C to +150C
-40
+85
C
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating -- plastic "N" package: - 12 mW/C from 65C to 85C.
DC Electrical Characteristics
Symbol VIH Parameter Minimum HIGH Level Input Voltage Conditions
TA = 25C Typ 1.5 3.15 4.2 0.5 1.35 1.8 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 8.0
TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 80 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 160
Units V V V V V V V V V V V V V V V V A A
Note 4: For a power supply of 5V 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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2
MM74HC393
AC Electrical Characteristics
VCC = 5V, TA = 25C, CL = 15 pF, tr = tf = 6 ns Symbol fMAX tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHL tREM tW Parameter Maximum Operating Frequency Maximum Propagation Delay, Clock A to QA Maximum Propagation Delay, Clock A to QB Maximum Propagation Delay, Clock A to QC Maximum Propagation Delay, Clock A to QD Maximum Propagation Delay, Clear to any Q Minimum Removal Time Minimum Pulse Width Clear or Clock Conditions Typ 50 13 19 23 27 15 -2 10 Guaranteed Limit 30 20 35 42 50 28 5 16 Units MHz ns ns ns ns ns ns ns
AC Electrical Characteristics
CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Maximum Operating Frequency tPHL, tPLH Maximum Propagation Delay Clock A to QA tPHL, tPLH Maximum Propagation Delay Clock A to QB tPHL, tPLH Maximum Propagation Delay Clock A to QC tPHL, tPLH Maximum Propagation Delay Clock to QD tPHL Maximum Propagation Delay Clear to any Q tREM Minimum Clear Removal Time tW Minimum Pulse Width Clear or Clock tTHL, tTLH Maximum Output Rise and Fall Time tr, tf Maximum Input Rise and Fall Time CPD CIN Power Dissipation Capacitance (Note 5) Maximum Input Capacitance 5 10 10 10 pF
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD V CC f + ICC.
Conditions
VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V
TA = 25C Typ 5 27 31 45 15 13 68 23 20 90 30 26 100 35 30 54 18 15 120 24 21 190 38 32 240 48 41 290 58 50 165 33 28 25 5 5 30 10 9 30 8 7 80 16 14 75 15 13 1000 500 400
TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 4 21 24 150 30 26 240 47 40 300 60 51 360 72 62 210 41 35 25 5 5 100 20 18 95 19 16 1000 500 400 3 18 20 180 35 31 285 57 48 360 72 61 430 87 75 250 49 42 25 5 5 120 24 20 110 22 19 1000 500 400
Units
MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF
(per counter)
42
3
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MM74HC393
Logic Timing Waveforms
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4
MM74HC393
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A
5
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MM74HC393
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
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6
MM74HC393
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
7
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MM74HC393 Dual 4-Bit Binary Counter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com


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